ChipFLOW — See how your hardware description becomes a design.
Write HDL, inspect synthesized logic, explore waveforms and examine physical-layout and analysis views.
Open ChipFLOW
Get to know ChipFLOW
ChipFLOW makes the stages of digital hardware design visible in one workspace. Move from an HDL description to a synthesized netlist, inspect the logic and explore its physical representation. Use waveform, timing, power and area views to understand the effects of design choices as you iterate.
Who it’s for
Digital designers, students and engineers exploring RTL, synthesis and physical-design workflows.
Describe the hardware
Write Verilog or VHDL in the editor and run the available synthesis flow. Inspect how the description maps into logic and standard cells.
Explore logic and signals
Follow connections in the RTL view and inspect waveform behavior. Use these views to investigate the structure and activity of a design.
Inspect physical layout
Explore cell placement and mask-layout views, including a 3D representation. Compare the physical organization with the logical design that produced it.
Understand design tradeoffs
Review the available timing, power, area and congestion information. Examine how different design choices affect these metrics within the selected flow and process assumptions.
A practical path through the work
Write the HDL
Start with a module or an example and define the design behavior.
Synthesize and inspect
Review the resulting logic, connections and waveforms.
Explore the implementation
Examine layout and analysis views to guide the next revision.
Available flows and analysis depend on the selected process and configuration. Layout visualization is not a substitute for foundry signoff.